A Reconfigurable Interconnect Network for a Piton Multi-chip System

Abstract

This project developed, tested and evaluated a reconfigurable interconnect network for a manycore multi-chip system based on the Princeton Piton Processor architecture framework. The system provides a full-stack solution for multi-chip routing from the off-chop router down to the inter-FPGA high-speed connection hardware. The main components of the system include a highly parameterizable off-chip outer that supports routing over different topologies, a high-speed interchip transceiver system leveraging the GTX serial transceiver on Xilinx 7-series FPGAs, and the extension PCBs that facilitate the high-radix interconnection across multiple FPGA boards. The design is targeted to be implementaed on multiple Digilent Genesys 2 boards using Kintex-7 FPGA. Challenges behind these objectives along with proposed and implemented solutions are also discussed in this report. Major challenges include but not limited to, designing parameterizable decision making rouiting logic in Verilog hardware description language, devising efficient workflow to generate interconnect networks of different sizes and topologies for evaluation , designing and interfacing with gigabit high-speed serial tranceivers, synchronization and flow control across multiple FPGA board, high speed PCB routing under layer number and space constrain, testing and evaluating a multi-FPGA system and etc.