TALON: An Adaptive Deadlock-free Routing Algorithm for Arbitrary Inter-chiplet Interconnect Topologies

Abstract

This project centers around the design of TALON, an adaptive, deadlock-free routing algorithm for arbitrary Network-on-Chip (NoC) and Inter-Chiplet Interconnect (ICI) topologies. As the semiconductor industry shifts towards 2.5D and 3D integration technologies, there is a demand for scalable interconnects that can support heterogeneous multi-chiplet layouts. Due to the flexibility that chiplets provide, these systems often feature irregular or sparse physical topologies that make traditional routing algorithms designed for symmetrical topologies impractical. The approach used in this work leverages a minimally adaptive routing mechanism that uses local congestion awareness and topology-aware route redirection. Experimental results demonstrate that TALON provides modest gains over deterministic routing algorithms like shortest-path routing while achieving superior performance over algorithms like spanning-tree routing.