Instruction-Level Abstraction for the Nvidia Deep Learning Accelerator: Planar Data Processing Unit

Abstract

Accelerators are commonly used in computing platforms alongside processors, and Instruction Level Abstraction (ILA) provides a valuable means of specifying accelerator operations while abstracting micro-architecture, enabling verification and end-user programming. This thesis presents the design and testing of part of the Instruction Level Abstraction (ILA) Model for Nvidia’s Deep Learning Accelerator (NVDLA), focusing on the Planar Data Processing Unit (PDP) or NVDLA Pooling Engine Block, which performs maximum, minimum, and average pooling. The ILA model was created by mapping PDP architectural states from NVDLA documentation, C and Verilog hardware models, and compiling a C++ SystemC model that was then tested to verify proper state updates and output. This thesis also covers the development and testing of configuration instructions for the Single Point Processor, which performs element-wise operations like bias addition, non-linear functions, batch normalization, and layer reduction.