Modeling Accelerators for Machine Learning Applications

Abstract

The objective of this research is to model with software the Instruction-Level Abstraction (ILA) of a hardware component known as an accelerator to allow for verification across the hardware-software divide. The target accelerator performs a machine learning algorithm known as Support-Vector Machine (SVM) using training parameters and kernel functions to classify and analyze data sets. The application of this accelerator is in a biomedical setting to reduce computational energy when analyzing sensor data from electrocardiographs, in the case of potential arrythmia, and electroencephalographs, in the case of potential seizure. The method for procuring the abstracted model of the SVMA includes creating a practice toy model, and then diving into Register-Transfer Level representation of the accelerator as well as its Finite-State Machines for each kernel mode. With a deep understanding of the functionality of the hardware, the ILA model will be written as an abstracted sequence of instructions. After the model is complete, the next step would be to test it thoroughly and ensure verifiability using Python. Index Terms – Instruction-Level Abstraction, Accelerator, Support-Vector Machine