The AI Kill Switch: Targeted Microarchitectural Limits to AI Performance

Abstract

AI is broadly utilized in computing today, but as models and agents grow more powerful, so too does the concern over whether AI can be aligned with human interests [1]. In particular, software-level mechanisms meant to control and manage AI models are insufficient, as AI models have already been shown to take steps to break rules in system prompts [2] and modify software to avoid being shutdown [3]. Conversely, hardware safeguards present a less malleable, more robust layer of protection against misaligned AI. We seek to develop hardware safeguards that limit the performance of an AI system such that its capabilities are significantly reduced. In this work, we conduct performance analysis on a GPU simulator [4], cutting hardware resources in the GPU memory hierarchy to analyze where cuts can be most effective. Through this analysis, we identify shared memory banks as a successful means of limiting performance, as cutting banks limits available shared memory bandwidth. We design, implement, and evaluate a microarchitectural mechanism in RTL for cutting shared memory banks available to GPU cores at runtime [5], and we propose next steps towards realizing a larger framework for control of AI models in hardware.